The present invention relates to flash memories and, more particularly, to a method of managing a flash memory, whose cells can be programmed with either one bit each or more than one bit each, so that the number of bits per cell can be determined upon power-up or during recovery from power loss.
Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the “1” state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. Now it is possible to read the stored bit by checking the threshold voltage of the cell—if the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage—all that is needed is to correctly identify in which of the two states the cell is currently located. For that purpose it is enough to make a comparison against a reference voltage value that is in the middle between the two states, and thus to determine if the cell's threshold voltage is below or above this reference value.
FIG. 1A shows graphically how this works. Specifically, FIG. 1A shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurities concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming” the flash memory.) Instead, the threshold voltage is distributed similar to the way shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages.
In recent years a new kind of flash device has appeared on the market, using a technique conventionally called “Multi Level Cells” or MLC for short. (This nomenclature is misleading, because the previous type of flash cells also have more than one level: they have two levels, as described above. Therefore, the two kinds of flash cells are referred to herein as “Single Bit Cells” (SBC) and “Multi-Bit Cells” (MBC).) The improvement brought by the MBC flash is the storing of two bits in each cell. (In principle MBC also includes the storage of more than two bits per cell, but such cells are not in the market yet at the present time. In order to simplify the explanations, the two-bit case is emphasized herein. It should however be understood the present invention is equally applicable to flash memory devices that support more than two bits per cell.) In order for a single cell to store two bits of information the cell must be able to be in one of four different states. As the cell's “state” is represented by its threshold voltage, it is clear an MBC cell should support four different valid ranges for its threshold voltage. FIG. 1B shows the threshold voltage distribution for a typical MBC cell. As expected, FIG. 1B has four peaks, each corresponding to one state. As for the SBC case, each state is actually a range and not a single number. When reading the cell's contents, all that must be guaranteed is that the range that the cell's threshold voltage is in is correctly identified. For a prior art example of an MBC flash device see U.S. Pat. No. 5,434,825 to Harari.
When encoding two bits in an MDC cell by the four states, it is common to have the left-most state in FIG. 1B (typically having a negative threshold voltage) represent the case of both bits having a value of “1”. (In the discussion below the following notation is used—the two bits of a cell are called the “lower bit” and the “upper bit”. An explicit value of the bits is written in the form [“upper bit” “lower bit”], with the lower bit value on the right. So the case of the lower bit being “0” and the upper bit being “1” is written as “10”. One must understand that the selection of this terminology and notation is arbitrary, and other names and encodings are possible). Using this notation, the left-most state represents the case of “11”. The other three states are typically assigned by the following order from left to right—“10”, “00”, “01”. One can see an example of an implementation of an MBC NAND flash device using such encoding as described above in U.S. Pat. No. 6,522,580 to Chen, which patent is incorporated by reference for all purposes as if fully set forth herein. See in particular FIG. 8 of the Chen patent. It should be noted though that the present invention does not depend on this assignment of the states, and any other ordering can be used, provided that the ordering satisfies the condition stated below. When reading an MBC cell's content, the range that the cell's threshold voltage is in must be identified correctly; only in this case this cannot always be achieved by comparing to one reference voltage, and several comparisons may be necessary. For example, in the case illustrated in FIG. 1B, one way to read the lower bit is first to compare the cell's threshold voltage to a reference comparison voltage V1 and then, depending on the outcome of the comparison, to compare the cell's threshold voltage to either a zero reference comparison voltage or a reference comparison voltage V2. Another way to read the lower bit is to compare the cell's threshold voltage unconditionally to both the zero reference voltage and V2. In either case, two comparisons are needed.
MBC devices provide a great advantage of cost—using a similarly sized cell one stores two bits rather than one. However, there are also some drawbacks to using MBC flash—the average read and write times of MDC memories are longer than of SLC memories, resulting in lower performance. Also, the reliability of MDC is lower than SBC. This can easily be understood—the differences between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leaking of the stored charge causing a threshold voltage drift, interference from operations on neighboring cells, etc.) that may have gone unnoticed in SBC because of the large gap between the two states, might cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower quality specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles. Thus there are advantages to using both MBC cells and SBC cells, and the selection can be different depending on the application's requirements.
It is obvious that a cell designed for MBC operation should also be able to operate as an SBC cell. After all, two states are just a subset of 4 states. Indeed, this idea already has appeared in the prior art—see for example U.S. Pat. No. 6,426,893 to Conley et al., where it is proposed to use both MBC and SBC modes within the same device, selecting certain parts of the device to operate with highest density in MBC mode, while other parts are used in SBC mode and provide better performance.
Other prior art goes even further—deciding on the mode a specific flash block operates in (whether MBC or SBC) dynamically during the application's run-time. For example, U.S. Pat. No. 5,930,167 to Lee et al. describes a system in which incoming data that has to be stored is first programmed in SBC mode so as to provide fast response time, and later is reprogrammed using MBC mode. The SBC mode thus provides a kind of caching mechanism. The second writing (done in MBC mode) can be done in the same place where the data was originally programmed in SBC mode, so it is clear the same area is dynamically switched between modes. Such programming in SBC mode vs. MBC mode is referred to herein as “N-bit programming”, with N=1 referring to SBC mode and N>1 referring to MBC mode.
However, such dynamic mode switching of flash blocks during run-time creates a problem. Think about what happens when power is unexpectedly removed from the device. When the power is later restored and the system's software starts running again, the system has to find out what mode was previously used for writing the data. Without knowing this, a wrong reading might result. FIGS. 1A and 1B illustrate why—suppose a cell was really programmed using 1-bit mode to contain a “0”, and the distribution is according to FIG. 1A. If the system mistakenly assumes the cell was programmed using 2-bit mode, the system will instruct the device to attempt a reading using 2-bit mode, which will cause the device circuitry to try to identify which of the four states exists. However, trying to distinguish between the two center states (“10” and “00” in our example) the flash circuitry might place the reference comparison voltage at a voltage value that is within the distribution range of the right-most state of the SBC cell. FIG. 1B shows such a case: reference comparison voltage V1 is exactly in the middle of the upper threshold voltage distribution of FIG. 1A. This means the result of this comparison and consequently the result of this reading cannot be predicted—in some cells the reading will return “10” and in others it will return “00”, even though all such cells were programmed to “0” in 1-bit mode. Such reading under the wrong mode produces unpredictable results. If such mistakes are allowed to take place, the contents of the storage device will become useless.
Similarly, if the distribution of threshold voltages in a 1-bit mode cell is as shown in FIG. 1C, if the system mistakenly assumes that the cell was programmed using 2-bit mode, when trying to distinguish between the two rightmost states (“00” and “01” in our example) the flash circuitry places reference comparison voltage V2 at a voltage value within the distribution of the right-most state of the SBC cell. Sometimes the presumed lower bit of the cell is read as “0”, and sometimes the presumed lower bit of the cell is read as “1”.
Obviously, one can defend against such mistakes by keeping in the storage device detailed tables in which it is specified which mode is used for writing each memory block. The table itself must be kept in a fixed predetermined mode and in a pre-known location, so that there are no mistakes in reading the table. But such a solution has very undesirable consequences. First, each “useful” write operation must now be accompanied by an “auxiliary” write for updating the table, resulting in lower write performance. Second, the complexity of the flash management software is significantly increased—protection must be provided against loss of the table due to a block becoming bad; protection must be provided against a power loss occurring in the middle of updating the table, etc.
There is thus a widely recognized need for, and it would be highly advantageous to have, an efficient way to tell which mode, SBC or MBC, was used to program a flash memory block that could have been programmed using either mode.